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Split the obs_o pins at occamy_chip and occamy_xilinx #88

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Konste11ation
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This PR splits the customized obs_t obs_o output at the occamy_chip and occamy_xilinx level to accommodate the requirements for the FPGA port definition.
The obs_t obs_o is splited to logic [7:0] obs_0_o obs_0_o, obs_1_o, obs_2_o,obs_3_o.

  1. The number of the obs pin is determined by the extra obs_num parameter in the tpl file and the python generator file.
  2. The width is determined by the extra obs_pin_width parameter in the tpl file and the python generator file.

I will also change the hemaia_top_chip to accommodate this change.

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@rgantonio rgantonio left a comment

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Before you push, kindly add new lines to each file. So that github is clean :)

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@IveanEx IveanEx left a comment

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Wait a moment! 😂😂This hardware is actually implemented already, but not yet merged😂 This is because the FPGA flow is currently under modification to adapt to our new debug daughterboard, so more tests are needed

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IveanEx commented Dec 2, 2024

This PR will be addressed in #93, with the verification on FPGA. So, I will close this PR.

@IveanEx IveanEx closed this Dec 2, 2024
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3 participants